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Espressif Systems /ESP32-P4 /SPI2 /SPI_DOUT_MODE

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Interpret as SPI_DOUT_MODE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_DOUT0_MODE)SPI_DOUT0_MODE 0 (SPI_DOUT1_MODE)SPI_DOUT1_MODE 0 (SPI_DOUT2_MODE)SPI_DOUT2_MODE 0 (SPI_DOUT3_MODE)SPI_DOUT3_MODE 0 (SPI_DOUT4_MODE)SPI_DOUT4_MODE 0 (SPI_DOUT5_MODE)SPI_DOUT5_MODE 0 (SPI_DOUT6_MODE)SPI_DOUT6_MODE 0 (SPI_DOUT7_MODE)SPI_DOUT7_MODE 0 (SPI_D_DQS_MODE)SPI_D_DQS_MODE

Description

SPI output delay mode configuration

Fields

SPI_DOUT0_MODE

The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
SPI_DOUT1_MODE

The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
SPI_DOUT2_MODE

The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
SPI_DOUT3_MODE

The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
SPI_DOUT4_MODE

The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
SPI_DOUT5_MODE

The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
SPI_DOUT6_MODE

The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
SPI_DOUT7_MODE

The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
SPI_D_DQS_MODE

The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data